LM3S5P3B Datasheet, PDF (860/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Universal Serial Bus (USB) Controller
18.4.1
The USB controller provides a method to set the current operating mode of the USB controller. This
register should be written with the desired default mode so that the controller can respond to external
USB events.
Endpoint Configuration
To start communication, the endpoint registers must first be configured. An endpoint must be
configured before enumerating to the Host controller.
The endpoint 0 configuration is limited because it is a fixed-function, fixed-FIFO-size endpoint. The
endpoint requires little setup but does require a software-based state machine to progress through
the setup, data, and status phases of a standard control transaction. The configuration of the
remaining endpoints is done once before enumerating and then only changed if an alternate
configuration is selected by the Host controller. Once the type of endpoint is configured, a FIFO
area must be assigned to each endpoint. In the case of bulk, control and interrupt endpoints, each
has a maximum of 64 bytes per transaction. Isochronous endpoints can have packets with up to
1023 bytes per packet. In either mode, the maximum packet size for the given endpoint must be
set prior to sending or receiving data.
Configuring each endpoint’s FIFO involves reserving a portion of the overall USB FIFO RAM to
each endpoint. The total FIFO RAM available is 4 Kbytes with the first 64 bytes reserved for endpoint
0. The endpoint’s FIFO must be at least as large as the maximum packet size. The FIFO can also
be configured as a double-buffered FIFO so that interrupts occur at the end of each packet and
allow filling the other half of the FIFO.
The USB Device controller's soft connect must be enabled when the Device is ready to start
communications, indicating to the Host controller that the Device is ready to start the enumeration
process.
18.5
Register Map
Table 18-6 on page 860 lists the registers. All addresses given are relative to the USB base address
of 0x4005.0000. Note that the USB controller clock must be enabled before the registers can be
programmed (see page 278). There must be a delay of 3 system clocks after the USB module clock
is enabled before any USB module registers are accessed.
Table 18-6. Universal Serial Bus (USB) Controller Register Map
Offset Name
Type
Reset
Description
0x000 USBFADDR
0x001 USBPOWER
0x002 USBTXIS
0x004 USBRXIS
0x006 USBTXIE
0x008 USBRXIE
0x00A USBIS
0x00B USBIE
0x00C USBFRAME
0x00E USBEPIDX
R/W
0x00
USB Device Functional Address
R/W
0x20
USB Power
RO
0x0000
USB Transmit Interrupt Status
RO
0x0000
USB Receive Interrupt Status
R/W
0xFFFF
USB Transmit Interrupt Enable
R/W
0xFFFE
USB Receive Interrupt Enable
RO
0x00
USB General Interrupt Status
R/W
0x06
USB Interrupt Enable
RO
0x0000
USB Frame Value
R/W
0x00
USB Endpoint Index
See
page
866
867
869
871
873
875
877
878
880
881
860
January 20, 2012
Texas Instruments-Production Data