LM3S5P3B Datasheet, PDF (7/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Stellaris^® LM3S5P3B Microcontroller
12.3.3 Hardware Sample Averaging Circuit ............................................................................. 548
12.3.4 Analog-to-Digital Converter .......................................................................................... 549
12.3.5 Differential Sampling ................................................................................................... 552
12.3.6 Internal Temperature Sensor ........................................................................................ 555
12.3.7 Digital Comparator Unit ............................................................................................... 555
12.4 Initialization and Configuration ..................................................................................... 560
12.4.1 Module Initialization ..................................................................................................... 560
12.4.2 Sample Sequencer Configuration ................................................................................. 561
12.5 Register Map .............................................................................................................. 561
12.6 Register Descriptions .................................................................................................. 563
13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 621
13.1 Block Diagram ............................................................................................................ 622
13.2 Signal Description ....................................................................................................... 622
13.3 Functional Description ................................................................................................. 624
13.3.1 Transmit/Receive Logic ............................................................................................... 624
13.3.2 Baud-Rate Generation ................................................................................................. 625
13.3.3 Data Transmission ...................................................................................................... 626
13.3.4 Serial IR (SIR) ............................................................................................................. 626
13.3.5 ISO 7816 Support ....................................................................................................... 627
13.3.6 Modem Handshake Support ......................................................................................... 627
13.3.7 LIN Support ................................................................................................................ 629
13.3.8 FIFO Operation ........................................................................................................... 630
13.3.9 Interrupts .................................................................................................................... 631
13.3.10 Loopback Operation .................................................................................................... 632
13.3.11 DMA Operation ........................................................................................................... 632
13.4 Initialization and Configuration ..................................................................................... 632
13.5 Register Map .............................................................................................................. 633
13.6 Register Descriptions .................................................................................................. 635
14 Synchronous Serial Interface (SSI) .................................................................... 685
14.1 Block Diagram ............................................................................................................ 686
14.2 Signal Description ....................................................................................................... 686
14.3 Functional Description ................................................................................................. 687
14.3.1 Bit Rate Generation ..................................................................................................... 688
14.3.2 FIFO Operation ........................................................................................................... 688
14.3.3 Interrupts .................................................................................................................... 688
14.3.4 Frame Formats ........................................................................................................... 689
14.3.5 DMA Operation ........................................................................................................... 696
14.4 Initialization and Configuration ..................................................................................... 697
14.5 Register Map .............................................................................................................. 698
14.6 Register Descriptions .................................................................................................. 699
15 Inter-Integrated Circuit (I²C) Interface ................................................................ 727
15.1 Block Diagram ............................................................................................................ 728
15.2 Signal Description ....................................................................................................... 728
15.3 Functional Description ................................................................................................. 729
15.3.1 I²C Bus Functional Overview ........................................................................................ 729
15.3.2 Available Speed Modes ............................................................................................... 731
15.3.3 Interrupts .................................................................................................................... 732
15.3.4 Loopback Operation .................................................................................................... 733
January 20, 2012
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