LM3S5P3B Datasheet, PDF (791/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Stellaris^® LM3S5P3B Microcontroller
Register 11: I²S Receive Interrupt Status and Mask (I2SRXISM), offset 0x810
This register indicates the receive interrupt status and interrupt masking control.
I2S Receive Interrupt Status and Mask (I2SRXISM)
Base 0x4005.4000
Offset 0x810
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
FFI
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
FFM
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:17
16
Name
reserved
FFI
Type
RO
RO
Reset
0x000
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Receive FIFO Service Request Interrupt
Value Description
0 The FIFO level is equal to or below the FIFO limit.
1 The FIFO level is above the FIFO limit.
15:1
reserved
RO
0x000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
FFM
R/W
0
FIFO Interrupt Mask
Value Description
0 The FIFO interrupt is masked and not sent to the CPU.
1 The FIFO interrupt is enabled to be sent to the interrupt
controller.
January 20, 2012
791
Texas Instruments-Production Data