LM3S5P3B Datasheet, PDF (30/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Table of Contents
Register 128: USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118 .............................. 910
Register 129: USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128 .............................. 910
Register 130: USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138 .............................. 910
Register 131: USB Receive Byte Count Endpoint 4 (USBRXCOUNT4), offset 0x148 .............................. 910
Register 132: USB Receive Byte Count Endpoint 5 (USBRXCOUNT5), offset 0x158 .............................. 910
Register 133: USB Receive Byte Count Endpoint 6 (USBRXCOUNT6), offset 0x168 .............................. 910
Register 134: USB Receive Byte Count Endpoint 7 (USBRXCOUNT7), offset 0x178 .............................. 910
Register 135: USB Receive Byte Count Endpoint 8 (USBRXCOUNT8), offset 0x188 .............................. 910
Register 136: USB Receive Byte Count Endpoint 9 (USBRXCOUNT9), offset 0x198 .............................. 910
Register 137: USB Receive Byte Count Endpoint 10 (USBRXCOUNT10), offset 0x1A8 .......................... 910
Register 138: USB Receive Byte Count Endpoint 11 (USBRXCOUNT11), offset 0x1B8 ........................... 910
Register 139: USB Receive Byte Count Endpoint 12 (USBRXCOUNT12), offset 0x1C8 .......................... 910
Register 140: USB Receive Byte Count Endpoint 13 (USBRXCOUNT13), offset 0x1D8 .......................... 910
Register 141: USB Receive Byte Count Endpoint 14 (USBRXCOUNT14), offset 0x1E8 .......................... 910
Register 142: USB Receive Byte Count Endpoint 15 (USBRXCOUNT15), offset 0x1F8 .......................... 910
Register 143: USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS), offset 0x340 ............. 912
Register 144: USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS), offset 0x342 ............ 914
Register 145: USB Device RESUME Raw Interrupt Status (USBDRRIS), offset 0x410 ............................ 916
Register 146: USB Device RESUME Interrupt Mask (USBDRIM), offset 0x414 ....................................... 917
Register 147: USB Device RESUME Interrupt Status and Clear (USBDRISC), offset 0x418 .................... 918
Register 148: USB DMA Select (USBDMASEL), offset 0x450 ................................................................ 919
Analog Comparators ................................................................................................................... 921
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 927
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 928
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 929
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 930
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 931
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 931
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 932
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 932
Pulse Width Modulator (PWM) .................................................................................................... 934
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 949
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 950
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 951
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 953
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 955
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 957
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 959
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 961
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 963
Register 10: PWM Fault Condition Value (PWMFAULTVAL), offset 0x024 ............................................ 965
Register 11: PWM Enable Update (PWMENUPD), offset 0x028 ........................................................... 967
Register 12: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 970
Register 13: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 970
Register 14: PWM2 Control (PWM2CTL), offset 0x0C0 ....................................................................... 970
Register 15: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 ..................................... 975
Register 16: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 ..................................... 975
Register 17: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 975
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January 20, 2012
Texas Instruments-Production Data