LM3S5P3B Datasheet, PDF (264/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

System Control
Register 29: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset
0x110
This register controls the clock gating logic in Sleep mode. Each bit controls a clock enable for a
given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC0 is the clock configuration register for
running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Sleep Mode Clock Gating Control Register 0 (SCGC0)
Base 0x400F.E000
Offset 0x110
Type R/W, reset 0x00000040
31
30
29
28
27
26
25
reserved
WDT1
reserved
Type RO
RO
RO
R/W
RO
RO
RO
Reset
0
0
0
0
0
0
0
24
CAN0
R/W
0
23
22
reserved
RO
RO
0
0
15
Type RO
Reset
0
14
13
reserved
RO
RO
0
0
12
11
10
9
8
7
6
MAXADC1SPD
MAXADC0SPD
reserved
HIB
RO
R/W
R/W
R/W
R/W
RO
R/W
0
0
0
0
0
0
1
21
20
PWM
RO
R/W
0
0
5
4
reserved
RO
RO
0
0
19
18
reserved
RO
RO
0
0
3
2
WDT0
R/W
RO
0
0
17
ADC1
R/W
0
16
ADC0
R/W
0
1
0
reserved
RO
RO
0
0
Bit/Field
31:29
28
27:25
24
23:21
Name
reserved
WDT1
reserved
CAN0
reserved
Type
RO
R/W
RO
R/W
RO
Reset
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT1 Clock Gating Control
This bit controls the clock gating for Watchdog Timer module 1. If set,
the module receives a clock and functions. Otherwise, the module is
unclocked and disabled. If the module is unclocked, a read or write to
the module generates a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN0 Clock Gating Control
This bit controls the clock gating for CAN module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
264
January 20, 2012
Texas Instruments-Production Data