LM3S5P3B Datasheet, PDF (25/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Stellaris^® LM3S5P3B Microcontroller
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Register 29:
UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 671
UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 672
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 673
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 674
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 675
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 676
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 677
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 678
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 679
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 680
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 681
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 682
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 683
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 684
Synchronous Serial Interface (SSI) ............................................................................................ 685
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 700
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 702
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 704
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 705
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 707
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 708
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 709
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 711
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 713
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 714
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 715
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 716
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 717
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 718
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 719
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 720
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 721
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 722
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 723
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 724
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 725
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 726
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 727
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 744
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 745
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 750
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 751
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 752
Register 6: I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 753
Register 7: I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 754
Register 8: I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 755
Register 9: I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 756
January 20, 2012
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