LM3S5P3B Datasheet, PDF (21/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Stellaris^® LM3S5P3B Microcontroller
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 341
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 342
Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 343
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 345
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 346
User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 347
User Register 3 (USER_REG3), offset 0x1EC ................................................................. 348
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 349
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 350
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 351
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 352
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 353
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 354
Micro Direct Memory Access (μDMA) ........................................................................................ 355
Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 378
Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 379
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 380
Register 4: DMA Status (DMASTAT), offset 0x000 ............................................................................ 385
Register 5: DMA Configuration (DMACFG), offset 0x004 ................................................................... 387
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 388
Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 389
Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 390
Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 391
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 392
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 393
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 394
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 395
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 396
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 397
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 398
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 399
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 400
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 401
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 402
Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 403
Register 22: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 404
Register 23: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 405
Register 24: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 406
Register 25: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 407
Register 26: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 408
Register 27: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 409
Register 28: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 410
Register 29: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 411
Register 30: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 412
General-Purpose Input/Outputs (GPIOs) ................................................................................... 413
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 427
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 428
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 429
January 20, 2012
21
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