|
LM3S5P3B Datasheet, PDF (55/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller | |||
|
◁ |
Stellaris® LM3S5P3B Microcontroller
1.3.4
each FIFO entry contains an 8-bit left and an 8-bit right sample, reducing memory requirements
further.
Both the transmitter and receiver are capable of being a master or a slave.
The Stellaris I2S interface has the following features:
â Configurable audio format supporting I2S, Left-justification, and Right-justification
â Configurable sample size from 8 to 32 bits
â Mono and Stereo support
â 8-, 16-, and 32-bit FIFO interface for packing memory
â Independent transmit and receive 8-entry FIFOs
â Configurable FIFO-level interrupt and µDMA requests
â Independent transmit and receive MCLK direction control
â Transmit and receive internal MCLK sources
â Independent transmit and receive control for serial clock and word select
â MCLK and SCLK can be independently set to master or slave
â Configurable transmit zero or last sample when FIFO empty
â Efficient transfers using Micro Direct Memory Access Controller (µDMA)
â Separate channels for transmit and receive
â Burst requests
â Channel requests asserted when FIFO contains required amount of data
System Integration
The LM3S5P3B microcontroller provides a variety of standard system functions integrated into the
device, including:
â Direct Memory Access Controller (DMA)
â System control and clocks including on-chip precision 16-MHz oscillator
â Three 32-bit timers (up to six 16-bit)
â Six Capture Compare PWM (CCP) pins
â Lower-power battery-backed Hibernation module
â Real-Time Clock in Hibernation module
â Two Watchdog Timers
â One timer runs off the main oscillator
â One timer runs off the precision internal oscillator
January 20, 2012
55
Texas Instruments-Production Data
|
▷ |