LM3S5P3B Datasheet, PDF (278/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

System Control
Register 34: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108
This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable
for a given interface, function, or module. If set, the module receives a clock and functions. Otherwise,
the module is unclocked and disabled (saving power). If the module is unclocked, reads or writes
to the module generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise
noted, so that all functional modules are disabled. It is the responsibility of software to enable the
ports necessary for the application. Note that these registers may contain more bits than there are
interfaces, functions, or modules to control. This configuration is implemented to assure reasonable
code compatibility with other family and future parts. RCGC2 is the clock configuration register for
running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the
ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep
modes.
Run Mode Clock Gating Control Register 2 (RCGC2)
Base 0x400F.E000
Offset 0x108
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
reserved
UDMA
reserved
Type RO
RO
R/W
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
24
23
22
21
20
19
18
17
16
reserved
USB0
RO
RO
RO
RO
RO
RO
RO
RO
R/W
0
0
0
0
0
0
0
0
0
8
GPIOJ
R/W
0
7
GPIOH
R/W
0
6
GPIOG
R/W
0
5
GPIOF
R/W
0
4
GPIOE
R/W
0
3
GPIOD
R/W
0
2
GPIOC
R/W
0
1
GPIOB
R/W
0
0
GPIOA
R/W
0
Bit/Field
31:17
16
15:14
13
12:9
Name
reserved
USB0
reserved
UDMA
reserved
Type
RO
R/W
RO
R/W
RO
Reset
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
USB0 Clock Gating Control
This bit controls the clock gating for USB module 0. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Micro-DMA Clock Gating Control
This bit controls the clock gating for micro-DMA. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
278
January 20, 2012
Texas Instruments-Production Data