LM3S5P3B Datasheet, PDF (26/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Table of Contents
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
I²C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 757
I²C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 758
I²C Slave Data (I2CSDR), offset 0x808 ........................................................................... 760
I²C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 761
I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 762
I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 763
I²C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 764
Inter-Integrated Circuit Sound (I²S) Interface ............................................................................ 765
Register 1: I²S Transmit FIFO Data (I2STXFIFO), offset 0x000 .......................................................... 778
Register 2: I²S Transmit FIFO Configuration (I2STXFIFOCFG), offset 0x004 ...................................... 779
Register 3: I²S Transmit Module Configuration (I2STXCFG), offset 0x008 .......................................... 780
Register 4: I²S Transmit FIFO Limit (I2STXLIMIT), offset 0x00C ........................................................ 782
Register 5: I²S Transmit Interrupt Status and Mask (I2STXISM), offset 0x010 ..................................... 783
Register 6: I²S Transmit FIFO Level (I2STXLEV), offset 0x018 .......................................................... 784
Register 7: I²S Receive FIFO Data (I2SRXFIFO), offset 0x800 .......................................................... 785
Register 8: I²S Receive FIFO Configuration (I2SRXFIFOCFG), offset 0x804 ...................................... 786
Register 9: I²S Receive Module Configuration (I2SRXCFG), offset 0x808 ........................................... 787
Register 10: I²S Receive FIFO Limit (I2SRXLIMIT), offset 0x80C ......................................................... 790
Register 11: I²S Receive Interrupt Status and Mask (I2SRXISM), offset 0x810 ..................................... 791
Register 12: I²S Receive FIFO Level (I2SRXLEV), offset 0x818 ........................................................... 792
Register 13: I²S Module Configuration (I2SCFG), offset 0xC00 ............................................................ 793
Register 14: I²S Interrupt Mask (I2SIM), offset 0xC10 ......................................................................... 795
Register 15: I²S Raw Interrupt Status (I2SRIS), offset 0xC14 ............................................................... 797
Register 16: I²S Masked Interrupt Status (I2SMIS), offset 0xC18 ......................................................... 799
Register 17: I²S Interrupt Clear (I2SIC), offset 0xC1C ......................................................................... 801
Controller Area Network (CAN) Module ..................................................................................... 802
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 823
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 825
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 828
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 829
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 830
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 831
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 833
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 834
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 834
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 835
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 835
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 838
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 838
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 839
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 839
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 841
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 841
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 842
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 842
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 844
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 844
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January 20, 2012
Texas Instruments-Production Data