LM3S5P3B Datasheet, PDF (858/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Universal Serial Bus (USB) Controller
USB controller continues and resynchronizes these pulses to the received SOF packets when these
packets are successfully received again.
18.3.1.8
USB RESET
When a RESET condition is detected on the USB bus, the USB controller automatically performs
the following actions:
■ Clears the USBFADDR register.
■ Clears the USB Endpoint Index (USBEPIDX) register.
■ Flushes all endpoint FIFOs.
■ Clears all control/status registers.
■ Enables all endpoint interrupts.
■ Generates a RESET interrupt.
When the application software driving the USB controller receives a RESET interrupt, any open
pipes are closed and the USB controller waits for bus enumeration to begin.
18.3.1.9
Connect/Disconnect
The USB controller connection to the USB bus is handled by software. The USB PHY can be
switched between normal mode and non-driving mode by setting or clearing the SOFTCONN bit of
the USBPOWER register. When the SOFTCONN bit is set, the PHY is placed in its normal mode,
and the USB0DP/USB0DM lines of the USB bus are enabled. At the same time, the USB controller
is placed into a state, in which it does not respond to any USB signaling except a USB RESET.
When the SOFTCONN bit is cleared, the PHY is put into non-driving mode, USB0DP and USB0DM are
tristated, and the USB controller appears to other devices on the USB bus as if it has been
disconnected. The non-driving mode is the default so the USB controller appears disconnected until
the SOFTCONN bit has been set. The application software can then choose when to set the PHY
into its normal mode. Systems with a lengthy initialization procedure may use this to ensure that
initialization is complete, and the system is ready to perform enumeration before connecting to the
USB bus. Once the SOFTCONN bit has been set, the USB controller can be disconnected by clearing
this bit.
Note: The USB controller does not generate an interrupt when the Device is connected to the
Host. However, an interrupt is generated when the Host terminates a session.
18.3.2
DMA Operation
The USB peripheral provides an interface connected to the μDMA controller with separate channels
for 3 transmit endpoints and 3 receive endpoints. Software selects which endpoints to service with
the μDMA channels using the USB DMA Select (USBDMASEL) register. The μDMA operation of
the USB is enabled through the USBTXCSRHn and USBRXCSRHn registers, for the TX and RX
channels respectively. When μDMA operation is enabled, the USB asserts a μDMA request on the
enabled receive or transmit channel when the associated FIFO can transfer data. When either FIFO
can transfer data, the burst request for that channel is asserted. The μDMA channel must be
configured to operate in Basic mode, and the size of the μDMA transfer must be restricted to whole
multiples of the size of the USB FIFO. Both read and write transfers of the USB FIFOs using μDMA
must be configured in this manner. For example, if the USB endpoint is configured with a FIFO size
of 64 bytes, the μDMA channel can be used to transfer 64 bytes to or from the endpoint FIFO. If the
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January 20, 2012
Texas Instruments-Production Data