LM3S5P3B Datasheet, PDF (497/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Stellaris^® LM3S5P3B Microcontroller
Bit/Field
9
8
7:5
4
3
Name
CBMRIS
TBTORIS
reserved
TAMRIS
RTCRIS
Type
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
Description
GPTM Timer B Capture Mode Match Raw Interrupt
Value Description
1 The capture mode match has occurred for Timer B. This interrupt
asserts when the values in the GPTMTBR and GPTMTBPR
match the values in the GPTMTBMATCHR and GPTMTBPMR
when configured in Input Edge-Time mode.
0 The capture mode match for Timer B has not occurred.
This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR
register.
GPTM Timer B Time-Out Raw Interrupt
Value Description
1 Timer B has timed out. This interrupt is asserted when a
one-shot or periodic mode timer reaches it's count limit (0 or
the value loaded into GPTMTBILR, depending on the count
direction).
0 Timer B has not timed out.
This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR
register.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer A Match Raw Interrupt
Value Description
1 The TAMIE bit is set in the GPTMTAMR register, and the match
value in the GPTMTAMATCHR and (optionally) GPTMTAPMR
registers have been reached when configured in one-shot or
periodic mode.
0 The match value has not been reached.
This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR
register.
GPTM RTC Raw Interrupt
Value Description
1 The RTC event has occurred.
0 The RTC event has not occurred.
This bit is cleared by writing a 1 to the RTCCINT bit in the GPTMICR
register.
January 20, 2012
497
Texas Instruments-Production Data