LM3S5P3B Datasheet, PDF (928/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Analog Comparators
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004
This register provides a summary of the interrupt status (raw) of the comparators. The bits in this
register must be enabled to generate interrupts using the ACINTEN register.
Analog Comparator Raw Interrupt Status (ACRIS)
Base 0x4003.C000
Offset 0x004
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IN1
IN0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:2
1
0
Name
reserved
IN1
IN0
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
0
Comparator 1 Interrupt Status
Value Description
1 Comparator 1 has generated an interruptfor an event as
configured by the ISEN bit in the ACCTL1 register.
0 An interrupt has not occurred.
This bit is cleared by writing a 1 to the IN1 bit in the ACMIS register.
RO
0
Comparator 0 Interrupt Status
Value Description
1 Comparator 0 has generated an interrupt for an event as
configured by the ISEN bit in the ACCTL0 register.
0 An interrupt has not occurred.
This bit is cleared by writing a 1 to the IN0 bit in the ACMIS register.
928
January 20, 2012
Texas Instruments-Production Data