LM3S5P3B Datasheet, PDF (14/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Table of Contents
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 5-9.
Table 6-1.
Table 6-2.
Table 6-3.
Table 6-4.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Revision History .................................................................................................. 33
Documentation Conventions ................................................................................ 43
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 71
Processor Register Map ....................................................................................... 72
PSR Register Combinations ................................................................................. 77
Memory Map ....................................................................................................... 85
Memory Access Behavior ..................................................................................... 88
SRAM Memory Bit-Banding Regions .................................................................... 90
Peripheral Memory Bit-Banding Regions ............................................................... 90
Exception Types .................................................................................................. 96
Interrupts ............................................................................................................ 97
Exception Return Behavior ................................................................................. 102
Faults ............................................................................................................... 102
Fault Status and Fault Address Registers ............................................................ 104
Cortex-M3 Instruction Summary ......................................................................... 106
Core Peripheral Register Regions ....................................................................... 109
Memory Attributes Summary .............................................................................. 112
TEX, S, C, and B Bit Field Encoding ................................................................... 115
Cache Policy for Memory Attribute Encoding ....................................................... 116
AP Bit Field Encoding ........................................................................................ 116
Memory Region Attributes for Stellaris Microcontrollers ........................................ 116
Peripherals Register Map ................................................................................... 117
Interrupt Priority Levels ...................................................................................... 144
Example SIZE Field Values ................................................................................ 172
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 176
JTAG_SWD_SWO Signals (108BGA) ................................................................. 177
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 178
JTAG Instruction Register Commands ................................................................. 183
System Control & Clocks Signals (100LQFP) ...................................................... 187
System Control & Clocks Signals (108BGA) ........................................................ 187
Reset Sources ................................................................................................... 188
Clock Source Options ........................................................................................ 195
Possible System Clock Frequencies Using the SYSDIV Field ............................... 198
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 198
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 199
System Control Register Map ............................................................................. 204
RCC2 Fields that Override RCC Fields ............................................................... 225
Hibernate Signals (100LQFP) ............................................................................. 292
Hibernate Signals (108BGA) .............................................................................. 293
Hibernation Module Clock Operation ................................................................... 299
Hibernation Module Register Map ....................................................................... 301
Flash Memory Protection Policy Combinations .................................................... 322
User-Programmable Flash Memory Resident Registers ....................................... 326
Flash Register Map ............................................................................................ 326
μDMA Channel Assignments .............................................................................. 357
Request Type Support ....................................................................................... 359
14
January 20, 2012
Texas Instruments-Production Data