LM3S5P3B Datasheet, PDF (205/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Stellaris^® LM3S5P3B Microcontroller
Table 5-8. System Control Register Map (continued)
Offset Name
Type
Reset
Description
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x144
0x150
0x154
0x170
0x190
0x1A0
RCGC1
RCGC2
SCGC0
SCGC1
SCGC2
DCGC0
DCGC1
DCGC2
DSLPCLKCFG
PIOSCCAL
PIOSCSTAT
I2SMCLKCFG
DC9
NVMSTAT
R/W
0x00000000 Run Mode Clock Gating Control Register 1
R/W
0x00000000 Run Mode Clock Gating Control Register 2
R/W
0x00000040 Sleep Mode Clock Gating Control Register 0
R/W
0x00000000 Sleep Mode Clock Gating Control Register 1
R/W
0x00000000 Sleep Mode Clock Gating Control Register 2
R/W
0x00000040 Deep Sleep Mode Clock Gating Control Register 0
R/W
0x00000000 Deep-Sleep Mode Clock Gating Control Register 1
R/W
0x00000000 Deep Sleep Mode Clock Gating Control Register 2
R/W
0x0780.0000 Deep Sleep Clock Configuration
R/W
0x0000.0000 Precision Internal Oscillator Calibration
RO
0x0000.0040 Precision Internal Oscillator Statistics
R/W
0x0000.0000 I2S MCLK Configuration
RO
0x00FF.00FF Device Capabilities 9 ADC Digital Comparators
RO
0x0000.0001 Non-Volatile Memory Information
5.5 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
See
page
269
278
264
272
280
267
275
282
229
231
233
234
258
260
January 20, 2012
205
Texas Instruments-Production Data