LM3S5P3B Datasheet, PDF (19/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Stellaris^® LM3S5P3B Microcontroller
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
Register 38:
Register 39:
Register 40:
Register 41:
Register 42:
Register 43:
Register 44:
Register 45:
Register 46:
Register 47:
Register 48:
Register 49:
Register 50:
Register 51:
Register 52:
Register 53:
Register 54:
Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 134
Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 134
Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 134
Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 134
Interrupt 52-54 Priority (PRI13), offset 0x434 ................................................................... 134
Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 136
Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 137
CPU ID Base (CPUID), offset 0xD00 ............................................................................... 139
Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 140
Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 143
Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 144
System Control (SYSCTRL), offset 0xD10 ....................................................................... 146
Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 148
System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 150
System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 151
System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 152
System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 153
Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 157
Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 163
Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 164
Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 165
MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 166
MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 167
MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 169
MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 170
MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 170
MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 170
MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 170
MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 172
MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 172
MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 172
MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 172
System Control ............................................................................................................................ 187
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 206
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 208
Register 3: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 209
Register 4: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 211
Register 5: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 213
Register 6: Reset Cause (RESC), offset 0x05C ................................................................................ 215
Register 7: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 217
Register 8: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 222
Register 9: GPIO High-Performance Bus Control (GPIOHBCTL), offset 0x06C ................................... 223
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 225
Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 228
Register 12: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 229
Register 13: Precision Internal Oscillator Calibration (PIOSCCAL), offset 0x150 ................................... 231
Register 14: Precision Internal Oscillator Statistics (PIOSCSTAT), offset 0x154 .................................... 233
Register 15: I²S MCLK Configuration (I2SMCLKCFG), offset 0x170 ..................................................... 234
January 20, 2012
19
Texas Instruments-Production Data