LM3S5P3B Datasheet, PDF (758/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Inter-Integrated Circuit (I²C) Interface
Register 11: I²C Slave Control/Status (I2CSCSR), offset 0x804
This register functions as a control register when written, and a status register when read.
Read-Only Status Register
I2C Slave Control/Status (I2CSCSR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
Offset 0x804
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
FBR TREQ RREQ
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:3
2
1
Name
reserved
FBR
TREQ
Type
RO
RO
RO
Reset Description
0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
First Byte Received
Value Description
1 The first byte following the slave’s own address has been
received.
0 The first byte has not been received.
This bit is only valid when the RREQ bit is set and is automatically cleared
when data has been read from the I2CSDR register.
Note: This bit is not used for slave transmit operations.
0
Transmit Request
Value Description
1
The I²C controller has been addressed as a slave transmitter
and is using clock stretching to delay the master until data has
been written to the I2CSDR register.
0 No outstanding transmit request.
0
RREQ
RO
0
Receive Request
Value Description
1
The I²C controller has outstanding receive data from the I²C
master and is using clock stretching to delay the master until
the data has been read from the I2CSDR register.
0 No outstanding receive data.
758
January 20, 2012
Texas Instruments-Production Data