LM3S5P3B Datasheet, PDF (788/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Inter-Integrated Circuit Sound (I²S) Interface
Bit/Field
26
25
24
23
22
21:16
15:10
9:4
Name
LRP
reserved
RM
reserved
MSL
reserved
SSZ
SDSZ
Type
R/W
Reset
1
Description
Left/Right Clock Polarity
Value Description
0 In Stereo mode, I2S0RXWS is high during the transmission of
the left channel data.
In Mono mode, data is read while the I2S0RXWS signal is low
(Right Channel).
1 In Stereo mode, I2S0RXWS is high during the transmission of
the right channel data.
In Mono mode, data is read while the I2S0RXWS signal is high
(Left Channel).
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0
Read Mode
This bit selects the mode in which the receive data is received and stored
in the FIFO.
Value Description
0 Stereo/Mono mode
I2SRXFIFOCFG FMM bit specifies Stereo or Mono FIFO read
behavior.
1 Compact Stereo mode
Left/Right sample packed. Refer to I2SRXFIFOCFG for 8/16-bit
sample size selection.
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0
SCLK Master/Slave
Value Description
0 The receiver is a slave and uses the externally driven
I2S0RXSCK and I2S0RXWS signals.
1 The receiver is a master and uses the internally generated
I2S0RXSCK and I2S0RXWS signals.
RO
0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0x1F Sample Size
This field contains the number of bits minus one in the sample.
R/W
0x1F System Data Size
This field contains the number of bits minus one during the high or low
phase of the I2S0RXWS signal.
788
January 20, 2012
Texas Instruments-Production Data