LM3S5P3B Datasheet, PDF (859/1170 Pages) Texas Instruments – Stellaris® LM3S5P3B Microcontroller

Stellaris^® LM3S5P3B Microcontroller
18.4
number of bytes to transfer is less than 64, then a programmed I/O method must be used to copy
the data to or from the FIFO.
If the DMAMOD bit in the USBTXCSRHn/USBRXCSRHn register is clear, an interrupt is generated
after every packet is transferred, but the μDMA continues transferring data. If the DMAMOD bit is set,
an interrupt is generated only when the entire μDMA transfer is complete. The interrupt occurs on
the USB interrupt vector. Therefore, if interrupts are used for USB operation and the μDMA is
enabled, the USB interrupt handler must be designed to handle the μDMA completion interrupt.
Care must be taken when using the μDMA to unload the receive FIFO as data is read from the
receive FIFO in 4 byte chunks regardless of value of the MAXLOAD field in the USBRXCSRHn
register. The RXRDY bit is cleared as follows.
Table 18-3. Remainder (MAXLOAD/4)
Value
0
1
2
3
Description
MAXLOAD = 64 bytes
MAXLOAD = 61 bytes
MAXLOAD = 62 bytes
MAXLOAD = 63 bytes
Table 18-4. Actual Bytes Read
Value
0
1
2
3
Description
MAXLOAD
MAXLOAD+3
MAXLOAD+2
MAXLOAD+1
Table 18-5. Packet Sizes That Clear RXRDY
Value
0
1
2
3
Description
MAXLOAD, MAXLOAD-1, MAXLOAD-2, MAXLOAD-3
MAXLOAD
MAXLOAD, MAXLOAD-1
MAXLOAD, MAXLOAD-1, MAXLOAD-2
To enable DMA operation for the endpoint receive channel, the DMAEN bit of the USBRXCSRHn
register should be set. To enable DMA operation for the endpoint transmit channel, the DMAEN bit
of the USBTXCSRHn register must be set.
See “Micro Direct Memory Access (μDMA)” on page 355 for more details about programming the
μDMA controller.
Initialization and Configuration
To use the USB Controller, the peripheral clock must be enabled via the RCGC2 register (see
page 278).
The initial configuration in all cases requires that the processor enable the USB controller and USB
controller’s physical layer interface (PHY) before setting any registers. The next step is to enable
the USB PLL so that the correct clocking is provided to the PHY.
January 20, 2012
859
Texas Instruments-Production Data