LM3S6110 Datasheet, PDF (9/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Stellaris^® LM3S6110 Microcontroller
List of Figures
Figure 1-1. Stellaris LM3S6110 Microcontroller High-Level Block Diagram ............................... 37
Figure 2-1. CPU Block Diagram ............................................................................................. 46
Figure 2-2. TPIU Block Diagram ............................................................................................ 47
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 49
Figure 2-4. Bit-Band Mapping ................................................................................................ 69
Figure 2-5. Data Storage ....................................................................................................... 70
Figure 2-6. Vector Table ........................................................................................................ 75
Figure 2-7. Exception Stack Frame ........................................................................................ 77
Figure 3-1. SRD Use Example ............................................................................................... 92
Figure 4-1. JTAG Module Block Diagram .............................................................................. 151
Figure 4-2. Test Access Port State Machine ......................................................................... 155
Figure 4-3. IDCODE Register Format ................................................................................... 161
Figure 4-4. BYPASS Register Format ................................................................................... 161
Figure 4-5. Boundary Scan Register Format ......................................................................... 162
Figure 5-1. Basic RST Configuration .................................................................................... 165
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 166
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 166
Figure 5-4. Power Architecture ............................................................................................ 169
Figure 5-5. Main Clock Tree ................................................................................................ 171
Figure 6-1. Flash Block Diagram .......................................................................................... 226
Figure 7-1. GPIO Port Block Diagram ................................................................................... 257
Figure 7-2. GPIODATA Write Example ................................................................................. 258
Figure 7-3. GPIODATA Read Example ................................................................................. 258
Figure 8-1. GPTM Module Block Diagram ............................................................................ 299
Figure 8-2. 16-Bit Input Edge Count Mode Example .............................................................. 303
Figure 8-3. 16-Bit Input Edge Time Mode Example ............................................................... 304
Figure 8-4. 16-Bit PWM Mode Example ................................................................................ 305
Figure 9-1. WDT Module Block Diagram .............................................................................. 335
Figure 10-1. UART Module Block Diagram ............................................................................. 359
Figure 10-2. UART Character Frame ..................................................................................... 360
Figure 10-3. IrDA Data Modulation ......................................................................................... 362
Figure 11-1. SSI Module Block Diagram ................................................................................. 400
Figure 11-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 403
Figure 11-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 404
Figure 11-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 404
Figure 11-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 405
Figure 11-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 406
Figure 11-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 406
Figure 11-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 407
Figure 11-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 408
Figure 11-10. MICROWIRE Frame Format (Single Frame) ........................................................ 408
Figure 11-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 409
Figure 11-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 410
Figure 12-1. Ethernet Controller ............................................................................................. 439
Figure 12-2. Ethernet Controller Block Diagram ...................................................................... 439
Figure 12-3. Ethernet Frame ................................................................................................. 441
June 18, 2012
9
Texas Instruments-Production Data