LM3S6110 Datasheet, PDF (10/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Table of Contents
Figure 12-4. Interface to an Ethernet Jack .............................................................................. 447
Figure 13-1. Analog Comparator Module Block Diagram ......................................................... 487
Figure 13-2. Structure of Comparator Unit .............................................................................. 488
Figure 13-3. Comparator Internal Reference Structure ............................................................ 489
Figure 14-1. PWM Unit Diagram ............................................................................................ 500
Figure 14-2. PWM Module Block Diagram .............................................................................. 501
Figure 14-3. PWM Count-Down Mode .................................................................................... 502
Figure 14-4. PWM Count-Up/Down Mode .............................................................................. 503
Figure 14-5. PWM Generation Example In Count-Up/Down Mode ........................................... 503
Figure 14-6. PWM Dead-Band Generator ............................................................................... 504
Figure 15-1. 100-Pin LQFP Package Pin Diagram .................................................................. 536
Figure 15-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 537
Figure 18-1. Load Conditions ................................................................................................ 566
Figure 18-2. JTAG Test Clock Input Timing ............................................................................. 568
Figure 18-3. JTAG Test Access Port (TAP) Timing .................................................................. 569
Figure 18-4. JTAG TRST Timing ............................................................................................ 569
Figure 18-5. External Reset Timing (RST) .............................................................................. 570
Figure 18-6. Power-On Reset Timing ..................................................................................... 570
Figure 18-7. Brown-Out Reset Timing .................................................................................... 570
Figure 18-8. Software Reset Timing ....................................................................................... 570
Figure 18-9. Watchdog Reset Timing ..................................................................................... 571
Figure 18-10. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 572
Figure 18-11. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 572
Figure 18-12. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 573
Figure 18-13. External XTLP Oscillator Characteristics ............................................................. 575
Figure D-1. Stellaris LM3S6110 100-Pin LQFP Package Dimensions ...................................... 602
Figure D-2. 100-Pin LQFP Tray Dimensions .......................................................................... 604
Figure D-3. 100-Pin LQFP Tape and Reel Dimensions ........................................................... 605
Figure D-4. Stellaris LM3S6110 108-Ball BGA Package Dimensions ....................................... 606
Figure D-5. 108-Ball BGA Tray Dimensions ........................................................................... 608
Figure D-6. 108-Ball BGA Tape and Reel Dimensions ............................................................ 609
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June 18, 2012
Texas Instruments-Production Data