LM3S6110 Datasheet, PDF (171/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Stellaris^® LM3S6110 Microcontroller
Figure 5-5 on page 171 shows the logic for the main clock tree. The peripheral blocks are driven by
the system clock signal and can be individually enabled/disabled. The PWM clock signal is a
synchronous divide of the system clock to provide the PWM circuit with more range (set with PWMDIV
in RCC).
Figure 5-5. Main Clock Tree
USEPWMDIV ^a
PWMDW ^a
MOSCDIS ^a
Main OSC
IOSCDIS^a
Internal
OSC
(12 MHz)
Internal
OSC
(30 kHz)
Hibernation
Module
(32.768 kHz)
XTAL^a
PWRDN ^b
PLL
(400 MHz)
÷4
OSCSRC^b,d
÷2
BYPASS ^b,d
÷ 25
USESYSDIV ^a,d
SYSDIV ^b,d
PWRDN
PWM Clock
System Clock
ADC Clock
÷ 50
CAN Clock
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
Note: The figure above shows all features available on all Stellaris® Fury-class devices. Not all peripherals may be
available on this device.
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the
divisor is applied. Table 5-5 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
June 18, 2012
171
Texas Instruments-Production Data