LM3S6110 Datasheet, PDF (468/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Ethernet Controller
Register 15: Ethernet PHY Management Register 0 – Control (MR0), address
0x00
This register enables software to configure the operation of the PHY layer. The default settings of
these registers are designed to initialize the Ethernet Controller to a normal operational mode without
configuration.
Ethernet PHY Management Register 0 – Control (MR0)
Base 0x4004.8000
Address 0x00
Type R/W, reset 0x3100
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT
reserved
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
Bit/Field
15
14
13
Name
RESET
LOOPBK
SPEEDSL
Type
R/W
R/W
R/W
Reset
0
0
1
Description
Reset Registers
When set, this bit resets the PHY layer registers to their default state
and reinitializes internal state machines. Once the reset operation has
completed, this bit is cleared by hardware.
Loopback Mode
When set, this bit enables the Loopback mode of operation. The receiver
ignores external inputs and receives the data that is transmitted by the
transmitter.
Speed Select
Value Description
1 Enables the 100 Mb/s mode of operation (100BASE-TX).
0 Enables the 10 Mb/s mode of operation (10BASE-T).
12
ANEGEN
R/W
1
Auto-Negotiation Enable
When set, this bit enables the auto-negotiation process.
11
PWRDN
R/W
0
Power Down
When set, this bit places the PHY layer into a low-power consuming
state. All data on the data inputs is ignored.
10
ISO
R/W
0
Isolate
When set, this bit isolates the transmit and receive data paths and
ignores all data being transmitted and received.
9
RANEG
R/W
0
Restart Auto-Negotiation
When set, this bit restarts the auto-negotiation process. Once the restart
has initiated, this bit is cleared by hardware.
468
June 18, 2012
Texas Instruments-Production Data