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LM3S6110 Datasheet, PDF (24/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller | |||
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Revision History
Table 1. Revision History (continued)
Date
January 2009
Revision Description
4660 â Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W.
â Clarification added as to what happens when the SSI in slave mode is required to transmit but there
is no data in the TX FIFO.
â Added "Hardware Configuration" section to Ethernet Controller chapter.
â Additional minor data sheet clarifications and corrections.
November 2008
4283
â Revised High-Level Block Diagram.
â Additional minor data sheet clarifications and corrections were made.
October 2008
4149
â Corrected values for DSOSCSRC bit field in Deep Sleep Clock Configuration (DSLPCLKCFG)
register.
â The FMA value for the FMPRE3 register was incorrect in the Flash Resident Registers table in the
Internal Memory chapter. The correct value is 0x0000.0006.
â In the Ethernet chapter, major improvements were made including a rewrite of the conceptual
information and the addition of new figures to clarify how to use the Ethernet Controller interface.
â Incorrect Comparator Operating Modes tables were removed from the Analog Comparators chapter.
August 2008
3447
â Added note on clearing interrupts to Interrupts chapter.
â Added Power Architecture diagram to System Control chapter.
â Additional minor data sheet clarifications and corrections.
July 2008
3108
â Corrected resistor value in ERBIAS signal description.
â Additional minor data sheet clarifications and corrections.
May 2008
2972
â As noted in the PCN, three of the nine Ethernet LED configuration options are no longer supported:
TX Activity (0x2), RX Activity (0x3), and Collision (0x4). These values for the LED0 and LED1 bit
fields in the MR23 register are now marked as reserved.
â As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use
the LDO output as the source of VDD25 input.
â As noted in the PCN, pin 41 (ball K3 on the BGA package) was renamed from GNDPHY to ERBIAS.
A 12.4-kΩ resistor should be connected between ERBIAS and ground to accommodate future device
revisions (see âFunctional Descriptionâ on page 441).
â Additional minor data sheet clarifications and corrections.
April 2008
2881
â The ÎJA value was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating
Characteristics chapter.
â Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of
1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock.
â Values for IDD_HIBERNATE were added to the "Detailed Power Specifications" table in the "Electrical
Characteristics" chapter.
â The "Hibernation Module DC Electricals" table was added to the "Electrical Characteristics" chapter.
â The maximum value on Core supply voltage (VDD25) in the "Maximum Ratings" table in the "Electrical
Characteristics" chapter was changed from 4 to 3.
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June 18, 2012
Texas Instruments-Production Data
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