LM3S6110 Datasheet, PDF (451/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Stellaris^® LM3S6110 Microcontroller
Bit/Field
2
1
0
Name
TXEMP
TXER
RXINT
Type
RO
RO
RO
Reset
0
0
Description
Transmit FIFO Empty
When set, indicates that the packet was transmitted and that the TX
FIFO is empty.
Transmit Error
When set, indicates that an error was encountered on the transmitter.
The possible errors that can cause this interrupt bit to be set are:
■ The data length field stored in the TX FIFO exceeds 2032 decimal
(buffer length - 16 bytes of header data). The frame is not sent when
this error occurs.
■ The retransmission attempts during the backoff process have
exceeded the maximum limit of 16 decimal.
0
Packet Received
When set, indicates that at least one packet has been received and is
stored in the receiver FIFO.
Writes
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK)
Base 0x4004.8000
Offset 0x000
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
reserved
PHYINT MDINT RXER
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
W1C
W1C
W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
19
18
17
16
RO
0
3
FOV
W1C
0
RO
RO
0
0
2
TXEMP
W1C
0
1
TXER
W1C
0
RO
0
0
RXINT
W1C
0
Bit/Field
31:7
6
5
4
3
Name
reserved
PHYINT
MDINT
RXER
FOV
Type
RO
W1C
W1C
W1C
W1C
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Clear PHY Interrupt
Setting this bit clears the PHYINT interrupt in the MACRIS register.
0
Clear MII Transaction Complete
Setting this bit clears the MDINT interrupt in the MACRIS register.
0
Clear Receive Error
Setting this bit clears the RXER interrupt in the MACRIS register.
0
Clear FIFO Overrun
Setting this bit clears the FOV interrupt in the MACRIS register.
June 18, 2012
451
Texas Instruments-Production Data