LM3S6110 Datasheet, PDF (551/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Stellaris^® LM3S6110 Microcontroller
Table 16-5. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PB1
D12
CCP2
I/O
TTL
GPIO port B bit 1.
I/O
TTL
Capture/Compare/PWM 2.
PD4
I/O
TTL
GPIO port D bit 4.
E1
CCP3
I/O
TTL
Capture/Compare/PWM 3.
E2
PD5
I/O
TTL
GPIO port D bit 5.
LDO
E3
-
Power Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. The LDO
pin must also be connected to the VDD25 pins at the board level
in addition to the decoupling capacitor(s).
E10
VDD33
-
Power Positive supply for I/O and some logic.
E11
CMOD0
I
TTL
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
PB0
E12
CCP0
I/O
TTL
GPIO port B bit 0.
I/O
TTL
Capture/Compare/PWM 0.
PD7
I/O
TTL
GPIO port D bit 7.
F1
C0o
O
TTL
Analog comparator 0 output.
F2
PD6
I/O
TTL
GPIO port D bit 6.
F3
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
F10
GND
-
Power Ground reference for logic and I/O pins.
F11
GND
-
Power Ground reference for logic and I/O pins.
F12
GND
-
Power Ground reference for logic and I/O pins.
PD0
I/O
TTL
GPIO port D bit 0.
G1
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PD1
I/O
TTL
GPIO port D bit 1.
G2
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
G3
VDD25
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals.
G10
VDD33
-
Power Positive supply for I/O and some logic.
G11
VDD33
-
Power Positive supply for I/O and some logic.
G12
VDD33
-
Power Positive supply for I/O and some logic.
H1
PD3
I/O
TTL
GPIO port D bit 3.
H2
PD2
I/O
TTL
GPIO port D bit 2.
H3
GND
-
Power Ground reference for logic and I/O pins.
H10
VDD33
-
Power Positive supply for I/O and some logic.
H11
RST
I
TTL
System reset input.
H12
PF1
I/O
TTL
GPIO port F bit 1.
XTALNPHY
O
TTL
Ethernet PHY XTALN 25-MHz oscillator crystal output. Connect
J1
this pin to ground when using a single-ended 25-MHz clock input
connected to the XTALPPHY pin.
J2
XTALPPHY
I
TTL
Ethernet PHY XTALP 25-MHz oscillator crystal input or external
clock reference input.
J3
GND
-
Power Ground reference for logic and I/O pins.
J10
GND
-
Power Ground reference for logic and I/O pins.
June 18, 2012
551
Texas Instruments-Production Data