LM3S6110 Datasheet, PDF (588/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRCR0, type R/W, offset 0x040, reset 0x00000000 (see page 222)
PWM
WDT
SRCR1, type R/W, offset 0x044, reset 0x00000000 (see page 223)
COMP2 COMP1 COMP0
SSI0
TIMER2 TIMER1 TIMER0
UART0
SRCR2, type R/W, offset 0x048, reset 0x00000000 (see page 225)
EPHY0
EMAC0
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Internal Memory
Flash Memory Control Registers (Flash Control Offset)
Base 0x400F.D000
FMA, type R/W, offset 0x000, reset 0x0000.0000
FMD, type R/W, offset 0x004, reset 0x0000.0000
FMC, type R/W, offset 0x008, reset 0x0000.0000
FCRIS, type RO, offset 0x00C, reset 0x0000.0000
OFFSET
DATA
DATA
WRKEY
COMT MERASE ERASE WRITE
FCIM, type R/W, offset 0x010, reset 0x0000.0000
PRIS
ARIS
FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000
PMASK AMASK
Internal Memory
Flash Memory Protection Registers (System Control Offset)
Base 0x400F.E000
USECRL, type R/W, offset 0x140, reset 0x18
PMISC AMISC
FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF
FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF
USER_DBG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE
NW
USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF
NW
USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF
NW
READ_ENABLE
READ_ENABLE
PROG_ENABLE
PROG_ENABLE
DATA
DATA
DATA
DATA
DATA
DATA
USEC
DBG1 DBG0
588
June 18, 2012
Texas Instruments-Production Data