LM3S6110 Datasheet, PDF (20/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Table of Contents
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x064 .................................................... 497
Pulse Width Modulator (PWM) .................................................................................................... 499
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 508
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 509
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 510
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 511
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 512
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 513
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 514
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 515
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 516
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 517
Register 11: PWM0 Interrupt Enable (PWM0INTEN), offset 0x044 ...................................................... 519
Register 12: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 521
Register 13: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 522
Register 14: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 523
Register 15: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 524
Register 16: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 525
Register 17: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 526
Register 18: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 527
Register 19: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 530
Register 20: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 533
Register 21: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 534
Register 22: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 535
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June 18, 2012
Texas Instruments-Production Data