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LM3S6110 Datasheet, PDF (31/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller | |||
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Stellaris® LM3S6110 Microcontroller
â IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
â Four-bit Instruction Register (IR) chain for storing JTAG instructions
â IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
â ARM additional instructions: APACC, DPACC and ABORT
â Integrated ARM Serial Wire Debug (SWD)
â Internal Memory
â 64 KB single-cycle flash
⢠User-managed flash block protection on a 2-KB block basis
⢠User-managed flash data programming
⢠User-defined and managed flash-protection block
â 16 KB single-cycle SRAM
â GPIOs
â 8-35 GPIOs, depending on configuration
â 5-V-tolerant in input configuration
â Fast toggle capable of a change every two clock cycles
â Programmable control for GPIO interrupts
⢠Interrupt generation masking
⢠Edge-triggered on rising, falling, or both
⢠Level-sensitive on High or Low values
â Bit masking in both read and write operations through address lines
â Pins configured as digital inputs are Schmitt-triggered.
â Programmable control for GPIO pad configuration
⢠Weak pull-up or pull-down resistors
⢠2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be
configured with an 18-mA pad drive for high-current applications
⢠Slew rate control for the 8-mA drive
⢠Open drain enables
⢠Digital input enables
â General-Purpose Timers
June 18, 2012
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Texas Instruments-Production Data
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