LM3S6110 Datasheet, PDF (519/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Stellaris^® LM3S6110 Microcontroller
Register 11: PWM0 Interrupt Enable (PWM0INTEN), offset 0x044
This register controls the interrupt generation capabilities of the PWM generator. The events that
can cause an interrupt are:
■ The counter being equal to the load register
■ The counter being equal to zero
■ The counter being equal to the comparator A register while counting up
■ The counter being equal to the comparator A register while counting down
■ The counter being equal to the comparator B register while counting up
■ The counter being equal to the comparator B register while counting down
Any combination of these events can generate either an interrupt.
PWM0 Interrupt Enable (PWM0INTEN)
Base 0x4002.8000
Offset 0x044
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:6
5
Name
reserved
IntCmpBD
Type
RO
R/W
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Interrupt for Counter=Comparator B Down
Value Description
1 A raw interrupt occurs when the counter matches the value in
the PWMnCMPB register value while counting down.
0 No interrupt.
4
IntCmpBU
R/W
0
Interrupt for Counter=Comparator B Up
Value Description
1 A raw interrupt occurs when the counter matches the value in
the PWMnCMPB register value while counting up.
0 No interrupt.
June 18, 2012
519
Texas Instruments-Production Data