LM3S6110 Datasheet, PDF (252/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

General-Purpose Input/Outputs (GPIOs)
7 General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G). The GPIO module supports 8-35
programmable input/output pins, depending on the peripherals being used.
The GPIO module has the following features:
■ 8-35 GPIOs, depending on configuration
■ 5-V-tolerant in input configuration
■ Fast toggle capable of a change every two clock cycles
■ Programmable control for GPIO interrupts
– Interrupt generation masking
– Edge-triggered on rising, falling, or both
– Level-sensitive on High or Low values
■ Bit masking in both read and write operations through address lines
■ Pins configured as digital inputs are Schmitt-triggered.
■ Programmable control for GPIO pad configuration
– Weak pull-up or pull-down resistors
– 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured
with an 18-mA pad drive for high-current applications
– Slew rate control for the 8-mA drive
– Open drain enables
– Digital input enables
7.1 Signal Description
GPIO signals have alternate hardware functions. Table 7-4 on page 255 and Table 7-5 on page 255
list the GPIO pins and the digital alternate functions. Other analog signals are 5-V tolerant and are
connected directly to their circuitry (C0-, C0+, C1-, C1+, C2-, C2+). These signals are configured
by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. The digital alternate hardware
functions are enabled by setting the appropriate bit in the GPIO Alternate Function Select
(GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control
(GPIOPCTL) register to the numeric enoding shown in the table below. Note that each pin must be
programmed individually; no type of grouping is implied by the columns in the table.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting
RST puts the pins back to their default state.
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June 18, 2012
Texas Instruments-Production Data