LM3S6110 Datasheet, PDF (568/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Electrical Characteristics
18.2.3 JTAG and Boundary Scan
Table 18-12. JTAG Characteristics
Parameter
No.
Parameter Parameter Name
Min
Nom
J1
f_TCK
TCK operational clock frequency
J2
t_TCK
TCK operational clock period
J3
t_{TCK_LOW}
TCK clock Low time
J4
t_{TCK_HIGH}
TCK clock High time
J5
t_{TCK_R}
TCK rise time
J6
t_{TCK_F}
TCK fall time
J7
t_{TMS_SU}
TMS setup time to TCK rise
J8
t_{TMS_HLD}
TMS hold time from TCK rise
J9
t_{TDI_SU}
TDI setup time to TCK rise
J10
t_{TDI_HLD}
TDI hold time from TCK rise
2-mA drive
0
-
100
-
-
t_TCK/2
-
t_TCK/2
0
-
0
-
20
-
20
-
25
-
25
-
23
J11
TCK fall to Data
t _{TDO_ZDV} ^{Valid from High-Z}
4-mA drive
8-mA drive
15
-
14
8-mA drive with slew rate control
18
2-mA drive
21
J12
t _{TDO_DV}
TCK fall to Data
Valid from Data
Valid
4-mA drive
8-mA drive
14
-
13
8-mA drive with slew rate control
18
2-mA drive
9
J13
TCK fall to High-Z
t _{TDO_DVZ} ^{from Data Valid}
4-mA drive
8-mA drive
7
-
6
8-mA drive with slew rate control
7
J14
t_TRST
TRST assertion time
J15
t_{TRST_SU}
TRST setup time to TCK rise
100
-
10
-
Max
10
-
-
-
10
10
-
-
-
-
35
26
25
29
35
25
24
28
11
9
8
9
-
-
Figure 18-2. JTAG Test Clock Input Timing
J2
J3
J4
TCK
J6
J5
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
568
June 18, 2012
Texas Instruments-Production Data