LM3S6110 Datasheet, PDF (538/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Signal Tables
16 Signal Tables
16.1
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register. All digital inputs are Schmitt triggered.
■ Signals by Pin Number
■ Signals by Signal Name
■ Signals by Function, Except for GPIO
■ GPIO Pins and Alternate Functions
■ Connections for Unused Signals
100-Pin LQFP Package Pin Tables
16.1.1 Signals by Pin Number
Table 16-1. Signals by Pin Number
Pin Number
1
2
Pin Name
NC
NC
VDDA
Pin Type
-
-
-
3
GNDA
-
4
5
NC
-
6
NC
-
LDO
-
7
8
VDD
-
9
GND
-
PD0
I/O
10
PWM0
O
PD1
I/O
11
PWM1
O
12
PD2
I/O
13
PD3
I/O
14
VDD25
-
15
GND
-
Buffer Type^a Description
-
No connect. Leave the pin electrically unconnected/isolated.
-
No connect. Leave the pin electrically unconnected/isolated.
Power
The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in “Recommended DC Operating
Conditions” on page 563, regardless of system implementation.
Power
The ground reference for the analog circuits ( Analog Comparators,
etc.). These are separated from GND to minimize the electrical
noise contained on VDD from affecting the analog functions.
-
No connect. Leave the pin electrically unconnected/isolated.
-
No connect. Leave the pin electrically unconnected/isolated.
Power
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater. The LDO
pin must also be connected to the VDD25 pins at the board level
in addition to the decoupling capacitor(s).
Power Positive supply for I/O and some logic.
Power Ground reference for logic and I/O pins.
TTL
GPIO port D bit 0.
TTL
PWM 0. This signal is controlled by PWM Generator 0.
TTL
GPIO port D bit 1.
TTL
PWM 1. This signal is controlled by PWM Generator 0.
TTL
GPIO port D bit 2.
TTL
GPIO port D bit 3.
Power
Positive supply for most of the logic function, including the
processor core and most peripherals.
Power Ground reference for logic and I/O pins.
538
June 18, 2012
Texas Instruments-Production Data