LM3S6110 Datasheet, PDF (3/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Stellaris^® LM3S6110 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 21
About This Document .................................................................................................................... 26
Audience .............................................................................................................................................. 26
About This Manual ................................................................................................................................ 26
Related Documents ............................................................................................................................... 26
Documentation Conventions .................................................................................................................. 27
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Architectural Overview .......................................................................................... 29
Product Features .......................................................................................................... 29
Target Applications ........................................................................................................ 36
High-Level Block Diagram ............................................................................................. 36
Functional Overview ...................................................................................................... 38
ARM Cortex™-M3 ......................................................................................................... 38
Motor Control Peripherals .............................................................................................. 39
Analog Peripherals ........................................................................................................ 39
Serial Communications Peripherals ................................................................................ 40
System Peripherals ....................................................................................................... 41
Memory Peripherals ...................................................................................................... 42
Additional Features ....................................................................................................... 42
Hardware Details .......................................................................................................... 42
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.5
2.5.1
2.5.2
2.5.3
The Cortex-M3 Processor ...................................................................................... 44
Block Diagram .............................................................................................................. 45
Overview ...................................................................................................................... 46
System-Level Interface .................................................................................................. 46
Integrated Configurable Debug ...................................................................................... 46
Trace Port Interface Unit (TPIU) ..................................................................................... 47
Cortex-M3 System Component Details ........................................................................... 47
Programming Model ...................................................................................................... 48
Processor Mode and Privilege Levels for Software Execution ........................................... 48
Stacks .......................................................................................................................... 48
Register Map ................................................................................................................ 49
Register Descriptions .................................................................................................... 50
Exceptions and Interrupts .............................................................................................. 63
Data Types ................................................................................................................... 63
Memory Model .............................................................................................................. 63
Memory Regions, Types and Attributes ........................................................................... 64
Memory System Ordering of Memory Accesses .............................................................. 65
Behavior of Memory Accesses ....................................................................................... 65
Software Ordering of Memory Accesses ......................................................................... 66
Bit-Banding ................................................................................................................... 67
Data Storage ................................................................................................................ 69
Synchronization Primitives ............................................................................................. 70
Exception Model ........................................................................................................... 71
Exception States ........................................................................................................... 72
Exception Types ............................................................................................................ 72
Exception Handlers ....................................................................................................... 75
June 18, 2012
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