LM3S6110 Datasheet, PDF (515/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Stellaris^® LM3S6110 Microcontroller
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C
This register provides a summary of the interrupt status of the PWM generator block. A bit set to 1
indicates that the generator block is asserting an interrupt. The individual interrupt status registers
must be consulted to determine the reason for the interrupt, and used to clear the interrupt. For the
fault interrupt, a write of 1 to that bit position clears the latched interrupt status.
PWM Interrupt Status and Clear (PWMISC)
Base 0x4002.8000
Offset 0x01C
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
IntFault
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IntPWM0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:17
16
15:1
0
Name
reserved
IntFault
reserved
IntPWM0
Type
RO
R/W1C
RO
RO
Reset
0x00
0
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault Interrupt Asserted
Indicates that the fault input is asserting an interrupt.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM0 Interrupt Status
Indicates if the PWM generator 0 block is asserting an interrupt.
June 18, 2012
515
Texas Instruments-Production Data