LM3S6110 Datasheet, PDF (556/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Signal Tables
Table 16-6. Signals by Signal Name (continued)
Pin Name
Pin Number Pin Type Buffer Type^a Description
SSI0Fss
L4
I/O
TTL
SSI module 0 frame signal
SSI0Rx
L5
I
TTL
SSI module 0 receive
SSI0Tx
M5
O
TTL
SSI module 0 transmit
SWCLK
A9
I
TTL
JTAG/SWD CLK.
SWDIO
B9
I/O
TTL
JTAG TMS and SWDIO.
SWO
A10
O
TTL
JTAG TDO and SWO.
TCK
A9
I
TTL
JTAG/SWD CLK.
TDI
B8
I
TTL
JTAG TDI.
TDO
A10
O
TTL
JTAG TDO and SWO.
TMS
B9
I/O
TTL
JTAG TMS and SWDIO.
TRST
A8
I
TTL
JTAG TRST.
TXON
L8
O
Analog TXON of the Ethernet PHY.
TXOP
M8
O
Analog TXOP of the Ethernet PHY.
U0Rx
L3
I
TTL
UART module 0 receive. When in IrDA mode, this signal has
IrDA modulation.
U0Tx
M3
O
TTL
UART module 0 transmit. When in IrDA mode, this signal has
IrDA modulation.
VCCPHY
C10
-
Power VCC of the Ethernet PHY.
D10
D11
VDD
L12
-
Power Positive supply for I/O and some logic.
VDD25
C3
-
Power Positive supply for most of the logic function, including the
D3
processor core and most peripherals.
F3
G3
VDD33
E10
-
Power Positive supply for I/O and some logic.
G10
G11
G12
H10
K7
K8
K9
VDDA
C6
-
Power The positive supply for the analog circuits (ADC, Analog
C7
Comparators, etc.). These are separated from VDD to
minimize the electrical noise contained on VDD from affecting
the analog functions. VDDA pins must be supplied with a
voltage that meets the specification in “Recommended DC
Operating Conditions” on page 563, regardless of system
implementation.
XTALNPHY
J1
O
TTL
Ethernet PHY XTALN 25-MHz oscillator crystal output.
Connect this pin to ground when using a single-ended 25-MHz
clock input connected to the XTALPPHY pin.
XTALPPHY
J2
I
TTL
Ethernet PHY XTALP 25-MHz oscillator crystal input or
external clock reference input.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
556
June 18, 2012
Texas Instruments-Production Data