LM3S6110 Datasheet, PDF (11/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Stellaris^® LM3S6110 Microcontroller
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 6-1.
Table 6-2.
Table 6-3.
Table 7-1.
Table 7-2.
Table 7-3.
Table 7-4.
Table 7-5.
Table 7-6.
Table 7-7.
Revision History .................................................................................................. 21
Documentation Conventions ................................................................................ 27
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 49
Processor Register Map ....................................................................................... 50
PSR Register Combinations ................................................................................. 55
Memory Map ....................................................................................................... 63
Memory Access Behavior ..................................................................................... 65
SRAM Memory Bit-Banding Regions .................................................................... 67
Peripheral Memory Bit-Banding Regions ............................................................... 67
Exception Types .................................................................................................. 73
Interrupts ............................................................................................................ 74
Exception Return Behavior ................................................................................... 78
Faults ................................................................................................................. 79
Fault Status and Fault Address Registers .............................................................. 80
Cortex-M3 Instruction Summary ........................................................................... 82
Core Peripheral Register Regions ......................................................................... 86
Memory Attributes Summary ................................................................................ 89
TEX, S, C, and B Bit Field Encoding ..................................................................... 92
Cache Policy for Memory Attribute Encoding ......................................................... 93
AP Bit Field Encoding .......................................................................................... 93
Memory Region Attributes for Stellaris Microcontrollers .......................................... 93
Peripherals Register Map ..................................................................................... 94
Interrupt Priority Levels ...................................................................................... 119
Example SIZE Field Values ................................................................................ 147
JTAG_SWD_SWO Signals (100LQFP) ................................................................ 151
JTAG_SWD_SWO Signals (108BGA) ................................................................. 152
JTAG Port Pins Reset State ............................................................................... 152
JTAG Instruction Register Commands ................................................................. 159
System Control & Clocks Signals (100LQFP) ...................................................... 163
System Control & Clocks Signals (108BGA) ........................................................ 163
Reset Sources ................................................................................................... 164
Clock Source Options ........................................................................................ 170
Possible System Clock Frequencies Using the SYSDIV Field ............................... 172
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 172
System Control Register Map ............................................................................. 175
RCC2 Fields that Override RCC fields ................................................................. 190
Flash Protection Policy Combinations ................................................................. 227
User-Programmable Flash Memory Resident Registers ....................................... 230
Flash Register Map ............................................................................................ 230
GPIO Pins With Non-Zero Reset Values .............................................................. 253
GPIO Pins and Alternate Functions (100LQFP) ................................................... 253
GPIO Pins and Alternate Functions (108BGA) ..................................................... 254
GPIO Signals (100LQFP) ................................................................................... 255
GPIO Signals (108BGA) ..................................................................................... 255
GPIO Pad Configuration Examples ..................................................................... 260
GPIO Interrupt Configuration Example ................................................................ 260
June 18, 2012
11
Texas Instruments-Production Data