LM3S6110 Datasheet, PDF (23/610 Pages) Texas Instruments – Stellaris® LM3S6110 Microcontroller

Stellaris^® LM3S6110 Microcontroller
Table 1. Revision History (continued)
Date
January 2010
Revision Description
6712 ■ In "System Control" section, clarified Debug Access Port operation after Sleep modes.
■ Clarified wording on Flash memory access errors.
■ Added section on Flash interrupts.
■ Clarified operation of SSI transmit FIFO.
■ Made these changes to the Operating Characteristics chapter:
– Added storage temperature ratings to "Temperature Characteristics" table
– Added "ESD Absolute Maximum Ratings" table
■ Made these changes to the Electrical Characteristics chapter:
– In "Flash Memory Characteristics" table, corrected Mass erase time
– Added sleep and deep-sleep wake-up times ("Sleep Modes AC Characteristics" table)
– In "Reset Characteristics" table, corrected units for supply voltage (VDD) rise time
October 2009
6462
■ Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers
because the module resets in 32-bit mode.
■ Made these changes to the Electrical Characteristics chapter:
– Removed V_SIH and V_SIL parameters from Operating Conditions table.
– Added table showing actual PLL frequency depending on input crystal.
– Changed the name of the t_{HIB_REG_WRITE} parameter to t_{HIB_REG_ACCESS}.
– Changed SSI set up and hold times to be expressed in system clocks, not ns.
July 2009
July 2009
5920
5902
Corrected ordering numbers.
■ Clarified Power-on reset and RST pin operation; added new diagrams.
■ Clarified explanation of nonvolatile register programming in Internal Memory chapter.
■ Added explanation of reset value to FMPRE0/1/2/3, FMPPE0/1/2/3, USER_DBG, and USER_REG0/1
registers.
■ Added description for Ethernet PHY power-saving modes.
■ Corrected the reset values for bits 6 and 7 in the Ethernet MR24 register.
■ Changed buffer type for WAKE pin to TTL and HIB pin to OD.
■ In ADC characteristics table, changed Max value for GAIN parameter from ±1 to ±3 and added E_IR
(Internal voltage reference error) parameter.
■ Additional minor data sheet clarifications and corrections.
April 2009
5367
■ Added JTAG/SWD clarification (see “Communication with JTAG/SWD” on page 157).
■ Added clarification that the PLL operates at 400 MHz, but is divided by two prior to the application
of the output divisor.
■ Added "GPIO Module DC Characteristics" table (see Table 18-4 on page 564).
■ Additional minor data sheet clarifications and corrections.
June 18, 2012
23
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