STE10A Datasheet, PDF (8/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Pin description
STE10/100A
Table 1.
Pin no.
Pin description
Name
Type
PCI bus interface
113
INTA#
O/D
114
RST#
I
116
PCI-CLK
I
117
GNT#
I
118
REQ#
O
O
119
PME#
OD
120,121 AD-31,30
123,124 AD-29,28
126,127 AD-27,26
1,2
AD-25,24
6,7
AD-23,22
9,10
AD-21,20
12,13
AD-19,18
15,16
AD-17,16
I/O
29,30
AD-15,14
32~35 AD-13~10
37
AD-9
41
AD-8
43,44
AD-7, 6
46,47
AD-5,4
49,50
AD-3,2
52,53
AD-1,0
Description
PCI interrupt request. STE10/100A asserts this signal when
one of the interrupt event is set.
PCI reset signal to initialize the STE10/100A. The RST signal
should be asserted for at least 100µs to ensure that the
STE10/100A completes initialization. During the reset period,
all the output pins of STE10/100A will be placed in a high-
impedance state and all the O/D pins are floated.
PCI clock input to STE10/100A for PCI bus functions. The
Bus signals are synchronized relative to the rising edge of
PCI-CLK PCI-CLK must operate at a frequency in the range
between 20MHz and 33MHz to ensure proper network
operation.
PCI bus granted. This signal indicates that the STE10/100A
has been granted ownership of the PCI bus as a result of a
bus request.
PCI bus request. STE10/100A asserts this line when it needs
access to the PCI Bus.
The power management event signal is an open drain, active
low signal. The STE10/100A will assert PME# to indicate that
a power management event has occurred.
When WOL (bit 18 of CSR18) is set, the STE10/100A is
placed in wake on LAN mode. While in this mode, the
STE10/100A will activate the PME# signal upon receipt of a
magic packet frame from the network.
In the wake on LAN mode, when LWS (bit 17 of CSR18) is
set, the LAN-wake signal follows HP’s protocol; otherwise, it
is IBM protocol.
Multiplexed PCI bus address/data pins
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