STE10A Datasheet, PDF (33/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STE10/100A
Registers and descriptors description
Table 6.
Bit #
Configuration registers description (continued)
Name
Description
Default RW type
New capabilities. Indicates whether the STE10/100A
provides a list of extended capabilities, such as PCI
power management.
Same as
20
NC
1: the STE10/100A provides the PCI management
function.
bit 19 of
CSR18
RO
0: the STE10/100A doesn’t provide new capabilities.
19~ 9
--- Reserved
Command system error response.
8
CSE ^{1: enable system error response. The STE10/100A}
1
R/W
will assert SERR# when it finds a parity error during
the address phase.
7
--- Reserved
Command parity error response.
0: disable parity error response. STE10/100A will
ignore any detected parity error and keep on
6
CPE operating. Default value is 0.
0
R/W
1: enable parity error response. STE10/100A will
assert system error (bit 13 of CSR5) when a parity
error is detected.
5~ 3
--- Reserved
Command master operation ability.
2
CMO ^{0: disable the STE10/100A bus master ability.}
1
R/W
1: enable the PCI bus master ability. Default value is
1 for normal operation.
Command memory space access.
1
CMSA 0: disable the memory space access ability.
1: enable the memory space access ability.
1
R/W
Command I/O space access.
0
CIOSA 0: enable the I/O space access ability.
1: disable the I/O space access ability.
1
R/W
R/W: Read and write able. RO: Read able only.
CR2 (offset = 08h), CC - Class code and revision number
31~24
BCC
Base class code. It means STE10/100A is a network
controller.
02h
RO
23~16
SC
Subclass code. It means STE10/100A is a fast
ethernet controller.
00h
RO
15~ 8
--- Reserved
7~4
RN
Revision number, identifies the revision number of
STE10/100A
Ah
RO
3~0
SN
Step number, identifies the STE10/100A steps
within the current revision
1h
RO
RO: Read only
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