STE10A Datasheet, PDF (54/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Registers and descriptors description
STE10/100A
Table 8.
Bit #
19
18
17~7
6
5
4
3~2
1
0
Control/status register description (continued)
Name
Description
Default RW type
Power management. Enables the STE10/100A
power management abilities. When this bit is set
into “0” the STE10/100A will set the Cap_Ptr
register to zero, indicating no PCI compliant
X
PM power management capabilities. The value of
RO
this bit will be mapped to NC (CR1 bit 20). In PCI ^{from EEPROM}
power management mode, the wake up frames
include “Magic Packet”, “Unicast”, and
“Muliticast”.
Wake on LAN mode enable. When this bit is set
to ‘1’, then the STE10/100A enters wake on LAN
mode and enters the sleep state.
Once the STE10/100A enters the sleep state, it
X
WOL remains there until: the wake up event occurs,
R/W
the WOL bit is cleared, or a reset (software or ^{from EEPROM}
hardware) happens.
In wake on LAN mode the wake-up frame is
“Magic Packet” only.
---
RWP
Reserved
Reset wake-up pattern data register pointer
0
R/W
Disable or enable the PAUSE function for flow
control. The default value of PAUSE is
determined by the result of auto-negotiation. The _{Depends on}
driver software can overwrite this bit to enable or
PAUSE _{disable it after the auto-negotiation has}
the result of
auto-
R/W
completed.
negotiation
0: PAUSE function is disabled.
1: PAUSE function is enabled
Receive threshold enable.
1: the receive FIFO threshold is enabled.
RTE _{0: disable the receive FIFO threshold selection in}
0
R/W
DRT (bits 3~2), and the receive threshold is set
to the default 64 bytes.
DRT
Drain receive threshold
00: 32 bytes (8 DW)
01: 64 bytes (16 DW)
10: store-and -forward
11: reserved
01
R/W
SINT Software interrupt.
0
R/W
ATUR
1: enable automatically transmit-underrun
recovery.
0
R/W
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