STE10A Datasheet, PDF (29/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STE10/100A
Functional description
D3_hot (Software visible D3)
When the STE10/100A is brought back to D0 from D3hot the software must perform a full
initialization.
The STE10/100A in the D3hot state responds to configuration cycles as long as power and
clock are supplied. This requires the device to perform an internal reset and return to a
power-up reset condition without the RST# pin asserted.
Table 3. Power stage
Device PCI bus
state state
Function
context
Clock
D0
B0
Full function context
in place
Full speed
Configuration
D1
B0, B1
maintained. No Tx Stopped to
and Rx except wake- full speed
up events
D2
B0, B1,
B2
Configuration
maintained. No Tx
and Rx
Stopped to
full speed
D3hot
B0, B1,
B2
Configuration lost,
full initialization
required upon return
to D0
Stopped to
full speed
D3cold
All configuration lost.
B3
Power-on defaults in
place on return to
No clock
D0
Power
Supported
actions to
function
Full Any PCI
power transaction
Supported
actions from
function
Any PCI
transaction or
interrupt
PCI
configuration
access
Only wake-up
events
PCI
configuration
access(B0, B1)
PCI
configuration
access(B0, B1)
No
power
Power-on reset
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