STE10A Datasheet, PDF (49/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STE10/100A
Registers and descriptors description
Table 8.
Bit #
9
8
7-3
2
1
0
Control/status register description (continued)
Name
Description
Default RW type
Magic packet received enable. The STE10/100A
will include the “Magic Packet Received” event in Default 1 if PM
MPRE
its set of wake-up events. If this bit is set,
STE10/100A will assert PMEST bit of PMR1
& WOL bits of
CSR 18 are
R/W
(CR49) after STE10/100A has received a Magic both enabled.
packet.
Link status changed enable. The STE10/100A
will include the “Link status changed” event in its
LSCE
set of wake-up events. If this bit is set,
STE10/100A will assert PMEST bit of PMR1
0
R/W
after STE10/100A has detected a link status
changed event.
--- Reserved
Wake-up frame received,
1: Indicates STE10/100A has received a wake-
WFR _{up frame. It is cleared by writing a 1 or upon}
X
R/W1C*
power-up reset. It is not affected by a hardware
or software reset.
Magic packet received,
1: Indicates STE10/100A has received a magic
MPR _{packet. It is cleared by writing a 1 or upon power-}
X
up reset. It is not affected by a hardware or
software reset.
R/W1C*
Link status changed,
1: Indicates STE10/100A has detected a link
LSC _{status change event. It is cleared by writing a 1}
or upon power-up reset. It is not affected by a
hardware or software reset.
X
R/W1C*
R/W1C*, Read only and write one cleared.
CSR14 (offset = 70h), WPDR – Wake-up pattern data register
Offset 31
16 15
8
7
0
0000h
Wake-up pattern 1 mask bits 31:0
0004h
Wake-up pattern 1 mask bits 63:32
0008h
Wake-up pattern 1 mask bits 95:64
000ch
Wake-up pattern 1 mask bits 127:96
0010h
0014h
0018h
CRC16 of pattern 1
Reserved
Wake-up pattern 2 mask bits 31:0
Wake-up pattern 2 mask bits 63:32
Wake-up
pattern 1
offset
001ch
Wake-up pattern 2 mask bits 95:64
0020h
Wake-up pattern 2 mask bits 127:96
49/82