STE10A Datasheet, PDF (39/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STE10/100A
Registers and descriptors description
4.2
PCI control/status registers
Table 7. PCI control/status registers list
Offset from
base address
of CSR
Index
Name
Descriptions
00h
CSR0
PAR
PCI access register
08h
CSR1
TDR
Transmit demand register
10h
CSR2
RDR Receive demand register
18h
CSR3
RDB Receive descriptor base address
20h
CSR4
TDB
Transmit descriptor base address
28h
CSR5
SR
Status register
30h
CSR6
NAR Network access register
38h
CSR7
IER
interrupt enable register
40h
CSR8
LPC
Lost packet counter
48h
CSR9
SPR
Serial port register
50h
CSR10
---
Reserved
58h
CSR11
TMR Timer
60h
CSR12
---
Reserved
68h
CSR13
WCSR Wake-up control/status register
70h
CSR14
WPDR Wake-up pattern data register
78h
CSR15
WTMR Watchdog timer
80h
CSR16
ACSR5 Status register 2
84h
CSR17
ACSR7 Interrupt enable register 2
88h
CSR18
CR
Command register
8ch
CSR19
PCIC PCI bus performance counter
90h
CSR20
PMCSR Power management command and status
94h
CSR21
---
Reserved
98h
CSR22
---
Reserved
9ch
CSR23
TXBR Transmit burst counter/time-out register
a0h
CSR24
FROM Flash(boot) ROM port
a4h
CSR25
PAR0 Physical address register 0
a8h
CSR26
PAR1 Physical address register 1
ach
CSR27
MAR0 Multicast address hash table register 0
b0h
CSR28
MAR1 Multicast address hash table register 1
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