STE10A Datasheet, PDF (18/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Functional description
STE10/100A
3.3.2
Transmit pre-fetch data flow
– Transmit FIFO size=2K-byte
– Two packets in the FIFO at the same time
– Meet the transmit min. back-to-back
Figure 10. Transmit pre-fetch data flow
Place the 1st packet data into host memory
Issue transmit demand
FIFO-to-host memory operation (1st packet)
Transmit enable
Place the 2nd packet data into host memory
Check point
FIFO-to-host memory operation (2nd packet)
Place the 3rd packet data into host memory
Check point
FIFO-to-host memory operation (3rd packet)
Transmit
threshold
1st packet
Check the
next packet
IFG
2nd packet
1st packet is
transmitted, check
the 3rd packet
Time
: handled by driver
: handled by STE10/100A
3.3.3
Transmit early interrupt scheme
Figure 11. Transmit normal interrupt and early interrupt comparison
Host to TX-FIFO memory
operation
Transmit data from FIFO to media
Normal interrupt after transmit
completed
Driver return buffer to upper layer
Early interrupt after host to TX-
FIFO operation completed
Driver return buffer to upper layer
PC00355
Time
: handled by driver
The saved time when transmit
early interrupt is implemented
: handled by STE10/100A
PC00356
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