STE10A Datasheet, PDF (47/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STE10/100A
Registers and descriptors description
Table 8. Control/status register description (continued)
Bit #
Name
Description
Transmit descriptor unavailable interrupt enable.
2
TDUIE ^{1: this bit in conjunction with NIE (bit 16 of}
CSR7) will enable the transmit descriptor
unavailable interrupt.
Transmit processor stopped interrupt enable.
1
TPSIE ^{1: this bit in conjunction with AIE (bit 15 of}
CSR7) will enable the transmit processor
stopped interrupt.
Transmit completed interrupt enable.
0
TCIE ^{1: this bit in conjunction with NIE (bit 16 of}
CSR7) will enable the transmit completed
interrupt.
CSR8 (offset = 40h), LPC - Lost packet counter
31~17
16
15~0
---
LPCO
LPC
Reserved
Lost packet counter overflow.
1: when lost packet counter overflow occurs.
Cleared after read.
Lost packet counter.
The counter is incremented whenever a packet
is discarded as a result of no host receive
descriptors being available. Cleared after read.
CSR9 (offset = 48h), SPR - Serial port register
31~15
14
13
12
11
10~4
3
2
---
SRC
SWC
---
SRS
---
SDO
SDI
Reserved
Serial EEPROM read control.
When set, enables read access from EEPROM,
when SRS (CSR9 bit 11) is also set.
Serial EEPROM write control.
When set, enables write access to EEPROM,
when SRS (CSR9 bit 11) is also set.
Reserved
Serial EEPROM select.
When set, enables access to the serial
EEPROM (see description of CSR9 bit 14 and
CSR9 bit 13).
Reserved
Serial EEPROM data out.
This bit serially shifts data from the EEPROM to
the STE10/100A.
Serial EEPROM data in.
This bit serially shifts data from the STE10/100A
to the EEPROM.
Default
0
0
0
0
0
0
0
0
1
1
RW type
R/W
R/W
R/W
RO/LH
RO/LH
R/W
R/W
R/W
RO
R/W
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