STE10A Datasheet, PDF (58/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Registers and descriptors description
STE10/100A
4.3
Note:
Transceiver(XCVR) registers
There are 11 16-bit registers supporting the transceiver portion of STE10/100A, including 7
basic registers defined according to clause 22 “Reconciliation Sublayer and Media
Independent Interface” and clause 28 “Physical Layer link signaling for 10 Mb/s and 100
Mb/s auto-negotiation on twisted pair” of the IEEE802.3u standard. In addition, 4 special
registers are provided for advanced chip control and status.
Since only double word access is supported for register R/W in the STE10/100A, the higher
word (bit 31~16) of the XCVR registers (XR0~XR10) should be ignored.
Table 9. Transceiver registers list
Offset from
base address Reg. index
of CSR
Name
Register descriptions
b4h
XR0
XCR XCVR control register
b8h
XR1
XSR XCVR status register
bch
XR2
PID1 PHY identifier 1
c0h
XR3
PID2 PHY identifier 2
c4h
XR4
ANA Auto-negotiation advertisement register
c8h
XR5
ANLPA Auto-negotiation link partner ability register
cch
XR6
ANE Auto-negotiation expansion register
d0h
XR7
XMC XCVR mode control register
d4h
XR8
XCIIS
XCVR configuration information and interrupt status
register
d8h
XR9
XIE XCVR interrupt enable register
dch
XR10
100CTR 100BASE-TX PHY control/status register
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