STE10A Datasheet, PDF (30/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Registers and descriptors description
4
Registers and descriptors description
STE10/100A
Note:
There are three kinds of registers within the STE10/100A: STE10/100A configuration
registers, PCI control/status registers, and transceiver control/status registers.
The STE10/100A configuration registers are used to initialize and configure the
STE10/100A and for identifying and querying the STE10/100A.
The PCI control/status registers are used to communicate between the host and
STE10/100A. The host can initialize, control, and read the status of the STE10/100A
through mapped I/O or memory address space.
The STE10/100A contains 11 16-bit registers to supported transceiver control and status.
They include 7 basic registers which are defined according to clause 22 “Reconciliation
Sub-layer and Media Independent Interface” and clause 28 “Physical Layer link signaling for
10 Mb/s and 100 Mb/s auto-negotiation on twisted pair” of the IEEE802.3u standard. In
addition, 4 special registers are provided for advanced chip control and status.
The STE10/100A also provides receive and transmit descriptors for packet buffering and
management.
4.1
STE10/100A configuration registers
An STE10/100A software driver can initialize and configure the chip by writing its
configuration registers. The contents of configuration registers are set to their default values
upon power-up or whenever a hardware reset occurs, but their settings remain unchanged
whenever a software reset occurs. The configuration registers are byte, word, and double
word accessible.
Table 4.
Offset
00h
04h
08h
0ch
10h
14h
2ch
30h
34h
3ch
40h
80h
c0h
c4h
STE10/100A configuration registers list
Index
Name
Description
CR0
LID Loaded device ID and vendor ID
CR1
CSC Configuration status and command
CR2
CC
Class code and revision number
CR3
LT
Latency timer
CR4
IOBA IO base address
CR5
MBA Memory base address
CR11
SID Subsystem ID and vendor ID
CR12
CR13
BRBA
CP
Boot ROM base address (ROM size = 128Kbit)
Capability pointer
CR15
CINT Configuration interrupt
CR16
DS
Driver space for special purpose
CR32
CR48
SIG
PMR0
Signature of STE10/100A
Power management register 0
CR49
PMR1 Power management register 1
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