STE10A Datasheet, PDF (56/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Registers and descriptors description
STE10/100A
Table 8. Control/status register description (continued)
Bit #
Name
Description
PowerState, this two-bit field is used both to
determine the current power state of the
STE10/100A and to set the STE10/100A into a
new power state. The definition of this field is
given below.
00b - D0
1,0
PWRS ^{01b - D1}
10b - D2
11b - D3hot
If software attempts to write an unsupported
state to this field, the write operation will
complete normally on the bus, but the data is
discarded and no state change occurs.
CSR23 (offset = 9ch), TXBR - Transmit burst count / time-out
31~21
20~16
15~12
11~0
--- Reserved
TBCNT
Transmit burst count
Specifies the number of consecutive successful
transmit burst writes to complete before the
transmit completed interrupt will be generated.
--- Reserved
TTO
Transmit time-out = (deferred time + back-off
time).
When TDIE (ACSR7 bit 28) is set, the timer is
decreased in increments of 2.56us (@100M) or
25.6us (@10M). If the timer expires before
another packet transmit begins, then the TDIE
interrupt will be generated.
CSR24 (offset = a0h), FROM - Flash ROM (also the boot ROM) port
31
30~28
27
26
25
24~8
7~0
This bit is only valid when 4 LEDmode_on
bra16_on
(CSR18 bit 23) is set. In this case, when
bra16_on is set, pin 87 functions as brA16;
otherwise it functions as LED pin – fd/col.
--- Reserved
REN
Read enable. Clear if read data is ready in DATA,
bit7-0 of FROM.
WEN Write enable. Cleared if write completed.
--- Reserved
ADDR Flash ROM address
DATA Read/Write data of flash ROM
Default
00b
1
0
1
0
1
0
0
0
0
RW type
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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