STE10A Datasheet, PDF (55/82 Pages) STMicroelectronics – PCI 10/100 Ethernet controller with integrated PHY (3.3V)

STE10/100A
Registers and descriptors description
Table 8.
Bit #
Control/status register description (continued)
Name
Description
CSR19 (offset = 8ch), PCIC - PCI bus performance counter
31~16
15~8
7~0
CLKCNT
The number of PCI clocks from read request
asserted to access completed. This PCI clock
count is accumulated for all the read command
cycles from the last CSR19 read to the current
CSR19 read.
--- Reserved
DWCNT
The number of double words accessed by the
last bus master. This double word count is
accumulated for all bus master data transactions
from the last CSR19 read to the current CSR19
read.
Default
0
0
RO* = Read only and cleared by reading.
CSR20 (offset = 90h), PMCSR - Power management command and status
(The same register value mapping to CR49-PMR1)
31~16
15
14,13
12~9
8
7~2
--- Reserved
PMES
PME_Status. This bit is set whenever the
STE10/100A detects a wake-up event,
regardless of the state of the PME-En bit.
Writing a “1” to this bit will clear it, causing the
STE10/100A to deassert PME# (if so enabled).
Writing a “0” has no effect.
DSCAL
Data_Scale. Indicates the scaling factor to be
used when interpreting the value of the data
register. This field is required for any function
that implements the data register.
The STE10/100A does not support data register
and Data_Scale.
DSEL
Data_Select. This four bit field is used to select
which data is to be reported through the data
register and Data_Scale field. This field is
required for any function that implements the
data register.
The STE10/100A does not support Data_select.
PME_En. When set, enables the STE10/100A to
PME_En assert PME#. When cleared, disables the PME#
assertion.
--- Reserved
0
00b
0000b
0
000000b
RW type
RO*
RO*
RO
RO
RO
RO
RO
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